1. Technical Field
The present disclosure relates to an interleaved analog-to-digital converter (ADC) and to a method of performing an analog-to-digital conversion.
2. Description of the Related Art
FIG. 1 illustrates an example of an interleaved ADC comprising four sub-converters ADC1 to ADC4. Each of the sub-converters is coupled to an input line 102 via a corresponding switch 104 to 107 controlled by a respective timing signal φ1 to φ4 having respective phase offsets. Thus each of the sub-converters ADC1 to ADC4 samples an input signal Vin on the input line 102 at a different time, and provides a corresponding output signal D1 to D4 to respective inputs of a multiplexer (MUX) 108. Multiplexer 108 generates an output data signal Dout on a line 110 by periodically selecting each of the output signals D1 to D4 in turn.
Thus, by providing the four time-interleaved sub-converters ADC 1 to ADC4, the input signal Vin can be sampled at four times the rate of a single ADC, and thus the sampling frequency Fs can be four times as high.
In order to obtain a high quality digital output signal Dout, it would be desirable that the sub-converters ADC1 to ADC4 are well matched with each other, for example in terms of their respective voltage offsets and gains. However, these parameters may vary, for example due to PVT (process, voltage, temperature) variations, or other factors.
In order to correct such miss-matches, one option would be to provide a calibration phase for each sub-converter. However, a problem with such a solution is that it involves an interruption in the operation of the interleaved ADC or a reduction in its sampling frequency, either of which is undesirable due to the resulting reduction in performance/quality of the interleaved ADC.
There are also technical problems in calibrating the sub-converters to efficiently correct a miss-match without introducing further noise.